PNP high-current, high-swing output stage and method

ABSTRACT

An amplifier output stage including a PNP transistor having an emitter coupled to a power rail and a collector coupled to an amplifier output. The PNP transistor is driven by an NPN transistor having a collector coupled to the base of the PNP transistor. A bias circuit produces a base-emitter voltage across the PNP transistor so that the PNP transistor will conduct a desired quiescent current. The bias circuit has an effective output impedance which is sufficiently large to form a pole in combination with a frequency compensation capacitor coupled to the collector of the PNP transistor, with the pole being located at a frequency beyond the unity-gain frequency of the amplifier.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to amplifier circuits and, inparticular, an output stage of an amplifier capable of providing highcurrents at output levels close to the power supply rail.

2. Description of Related Art

There is an increasing demand for amplifier circuits having thecapability of accepting input signals that come very close to the upperand lower supply voltages and capable of providing outputs which havethe same capability. This is especially true in those application wherethe power supply voltages are small.

FIG. 1A is a schematic diagram of part of a conventional amplifieroutput. A PNP output transistor QA has an emitter coupled to thepositive supply voltage VCC and a collector coupled to the amplifieroutput. Thus, transistor QA is capable of sourcing current to a load.Although not shown, there is typically another device connected to theoutput for sinking current from a load.

PNP transistor QA is driven by a pair of Darlington-connected NPNtransistors QB and QC. A resistor RA is connected between the base andemitter of transistor QA. When driven hard, transistor QA is capable ofbecoming saturated so that the output can be pulled up within onesaturation voltage of the positive supply VCC. Since the saturationvoltage is typically on the order of tenths of a volt, the FIG. 1Acircuit is capable of providing a high voltage swing, a very desirablefeature in many applications.

The FIG. 1A circuit does posses certain shortcomings. By way of example,the settling time of the circuit is poor due to the high overalltransconductance (gm) of the circuit. Further, the gam of the circuitchanges significantly with changes in output current thereby making thecircuit difficult to stabilize.

FIG. 2A is a schematic diagram of a portion of an alternative prior artoutput stage. Again, the output stage utilizes a PNP transistor QDhaving an emitter coupled to the positive supply VCC and a collectorcoupled to the output. Thus, the output is capable of swing up to almostthe positive power supply VCC level. Transistor QD is driven by a pairof Darlington-connected NPN transistors QG and QF. A second PNPtransistor QE is connected as a diode, with the base and emitter of QEbeing connected to the base and emitter of transistor QD, respectively.

The FIG. 1B circuit is an improvement over the FIG. 1A circuit in thatthe current gain is reduced by the presence of QE. Transistors QD and QEform a current mirror circuit, with the ratio of the currents limitingthe current gain to a value substantially less than the current gain oftransistor QD alone. The current ratio is determined by the ratio of theemitter areas of QE and QB, with QD typically being ten times as largeas that of QB. Further, the slew rate or settling time of the circuit isimproved over that of the FIG. 1A circuit.

Capacitor CA provides of Miller capacitor feedback which operates tostabilize the circuit. However, the impedance is so low at the base oftransistor QE, the Miller capacitor feedback is not very effective. Thismakes the FIG. 1B circuit difficult to stabilize, particularly for largecapacitive loads.

There is a need for an amplifier output stage capable of providing ahigh voltage swing and yet can be easily stabilized for a wide range ofload currents and load capacitance. As will become apparent to thoseskilled in the art upon a reading of the following Detailed Descriptionof the Invention together with the drawings, the present inventionprovides these and other advantages.

SUMMARY OF THE INVENTION

An amplifier output stage of an amplifier, including a PNP transistorhaving a collector coupled to an amplifier output and an emitter coupledto a first power supply rail. A second transistor, an NPN transistor, isincluded having a base for receiving an input signal and a collectorcoupled to the base of the first PNP transistor. The output stageincludes a frequency compensation capacitor having one terminal coupledthe PNP transistor. A bias circuit is included which produces a biasvoltage across the base-emitter junction of the PNP transistor. The biasvoltage is independent of current flow through the PNP transistor andcauses the PNP transistor to conduct a desired quiescent current. Thebias circuit has an effective output impedance sufficiently large toform a pole in combination with the frequency compensation capacitor ata frequency beyond the unity-gain frequency of the amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are schematic diagrams of part of conventional amplifieroutput stages.

FIG. 2 is a schematic diagram of a amplifier circuit which includes anamplifier output stage in accordance with one embodiment of the presentinvention.

FIG. 3 is a schematic diagram of a detailed implementation of the commonmode feedback circuit used in the FIG. 2 amplifier output circuit.

FIG. 4 is a cross-section of a conventional PNP transistor structureused as one of the output transistors of the FIG. 2 amplifier outputstage.

FIG. 5 is a schematic diagram of an equivalent circuit of the FIG. 4transistor structure.

FIG. 6 is an alternative circuit arrangement for current gain limitingof the FIG. 2 amplifier output stage.

DETAILED DESCRIPTION OF THE INVENTION

Referring again to the drawings, FIG. 2 is a schematic diagram of anamplifier circuit 10 which incorporates one embodiment of the subjectoutput stage. It will be appreciated that other implementations ofoutput stages in accordance with the present invention can be made.

Amplifier circuit 10 includes an input stage capable of operating withdifferential input Vin+ and Vin− operating close to the power supplyrails VCC and VEE. The input stage includes NPN transistors Q1A and Q1Bconnected as a differential pair together with a tail current source I1.PNP transistors Q2A and Q2B form a second differential pair connected toa tail current source I2. The common bases of transistors Q1A and Q2Aare connected to receive input Vin+, with the common based oftransistors Q2A and Q2B being connected to received input Vin−.

Although not depicted, tail current steering circuitry operates to sensethe common mode input voltage, (Vin++Vin−)/2, and turn off source I2when the common mode input voltage is in the upper region of the voltagerange defined by VCC and VEE and to turn off source I1 when the commonmode voltage is in the lower region of the range. Thus, current outputsIN1+ and IN1− of differential pair Q2A and Q2B drop to zero when thecommon mode input voltage is in the upper range so that differentialpair Q2A and Q2B are inactive. Similarly, current outputs IN2+ and IN2−of differential pair Q1A and Q1B drop to zero when the common mode inputvoltage is in the lower half of the voltage range thereby renderingdifferential pair Q1A and Q1B inactive.

The intermediate stage following the input stage is sometimes referredto as a cascode dual input turn-around stage. The output stage followingthe intermediate stage is implemented in accordance with one embodimentof the present invention.

The intermediate stage includes a pair of PNP transistors Q3A and Q3Bconnected in a common base configuration for level shifting currentsIN2+ and IN2−. Transistors Q3A and Q3B are connected in series withresistors R1A and R1B, respectively, and are biased by voltage Vbias foroperation close to upper supply voltage VCC. Voltage Vbias is producedby a PNP transistor Q14 which is connected as a diode. A resistor R15 isconnected intermediate the emitter of Q14 and positive supply VCC.

The intermediate stage further includes a pair of NPN transistors Q4Aand Q4B connected in a common base configuration for level shiftingcurrents IN1+ and IN1−. Resistors R2A and R2B are connected in serieswith transistors Q4A and Q4B, respectively, with the transistors beingbiased by the output of a common mode feedback circuit to be described.

One-half of the differential output of the turn around stage isconnected to the base of emitter-follower configured NPN transistor Q5.The other half of the differential output is connected to the base ofemitter-follower configured transistor Q6. A pair of equal valueresistors R5 and R6 are connected in series between the emitters oftransistors Q5 and Q6 so that the voltage intermediate the resistors isindicative of the common mode voltage of the intermediate stage. Theintermediate voltage is connected to the input of a buffer circuit A1,the output of which is connected to a level shifting element VA. Theoutput of element VA is connected to the common bases of transistors Q4Aand Q4B so as to provided a common mode feedback path. The feedbackmaintains transistors Q4A and Q4B in the active region and ensures thatQ3A and Q4A have equal collector currents and that Q3B and Q4B haveequal collector currents. Further details of the construction of bufferA1 and level shifter VA will be provided later.

The output of emitter-follower configured transistor Q6 is connected tothe base of output NPN transistor Q8. The collector of output transistorQ8 is connected to the output of the amplifier circuit 10 where Vout isproduced. Transistors Q6 and Q7 provide current gain for the negativeswing of Vout. Transistors Q5 and Q7 drive output PNP transistor Q9 andprovide current gain for the positive swing of Vout. Output transistorQ9 is shown in FIG. 2 with the primary PNP transistor Q9A and anassociated parasitic transistor Q9X. As will be explained in greaterdetail, current flow associated with parasitic transistor Q9X is used toprevent transistor Q9 from becoming deeply saturated.

It is desirable that the output stage have the same current gain whensourcing and sinking current. A significant difference in gain canrender the amplifier using the output stage difficult to stabilize.Transistors Q6 and Q8 determine the current gain when sinking current,with the gain being approximately equal to the product of the gain ofeach transistor. The transistors that would normally determine thecurrent gain when sourcing current include Q5, Q7 and Q9. PNP transistorQ10 is provided for limiting the current gain of Q9 so that the sinkingcurrent gain is closer to the sourcing current gain. A resistor R9 isconnected between the emitter of Q10 and supply VCC, with the collectorof Q10 being connected between the emitter of Q7 and a resistor R10.Increased current flow through Q7 tends to turn on transistor Q10 harderthereby increasing the voltage drop across resistor R10. Once theincrease in voltage at the emitter of Q7 becomes large with respect tothe value of kT/q, transistor Q7 will tend to turn off therebydecreasing base drive to output transistor Q9. This local feedback thuslimits the current gain at high output sourcing currents and has noeffect at lower currents. Resistor R12 connected between the emitter ofQ9 and power supply VCC represents the various ballast resistorsassociated with the individual transistors which make up largetransistor Q9. As is well known, these individual ballast resistorsensure that current flow is evenly distributed among the individualtransistors. Resistor R9 connected between the emitter of transistor Q10and VCC operates to compensate for the voltage drop across resistor R12.In order to reduce power consumption, transistor Q10 has an emitter areawhich is typically {fraction (1/10)} that of transistor Q9.

The quiescent current through output transistors Q8 and Q9 is wellcontrolled since the base-emitter voltages of the two transistors areboth defined. In the present case, the amplifier operates as a Class ABoutput, with there being a quiescent current typically of 250 μA and apeak output current of typically 100 mA.

The FIG. 2 output stage provides current limiting with no loss involtage swing of Vout. When the output stage is sinking a large amountof current from a load through transistor Q8, transistor Q6 is driven onas much as possible , with transistor Q5 being shut off. The common modefeedback provided by buffer A1 and related circuitry operates tomaintain the buffer input at the node intermediate resistors R5 and R6at a constant voltage in order to ensure that transistors Q4A and Q4Bare biased correctly. Since transistor Q5 is off, all of the currentdrawn by current source I5 is drawn through resistors R5 and R6.Transistor Q6 is the source of the current flow through R5 and R6. Underquiescent conditions, there is negligible current flow through resistorsR5 and R6. Given that the voltage at the node between resistors R5 andR6 remains constant, the base-emitter voltage of transistor Q8 willincrease by the increase in voltage drop across R6 (I5×R6) fromquiescent operation to current limit. Since the maximum base-emittervoltage of transistor Q8 is thus defined, the current limit point of Q8is also defined.

When the output stage is sourcing the maximum amount of current to aload by way of transistor Q9, transistor Q6 is off and transistor Q5 isdriven on as much as possible. Thus, resistors R5 and R6 conduct all ofthe current drawn by current source I4. The emitter voltage oftransistor Q5 will increase by a voltage equal to the increase involtage across resistor R5 (I4×R5). Again, since the maximumbase-emitter voltage of Q5 is set, the maximum current through thetransistor is set. Note that the change emitter voltage of transistor Q7when transistor Q10 begins conducting so as to reduce the current gainhas only a negligible effect on the operation of the current limitfunction provided by resistor R5 and current source I4.

FIG. 3 is a schematic diagram showing one implementation of the bufferA1 and the level shifting circuit VA. The buffer circuit includes anemitter-follower configured NPN transistor Q12 having a base connectedto the node intermediate resistors R5 and R6 and an emitter connected tosupply VEE by way of resistor R13. The output of the buffer A1 is theconnected to the emitter of a diode-connected transistor Q13. A constantcurrent source I5 provides a constant current that flows through aresistor R14 and transistor Q13 so the base-emitter voltage of Q12 iscanceled by the base-emitter voltage of transistor Q13. Thus, thevoltage applied to the common bases of transistors Q4A and Q4B is equalto the voltage at the node intermediate resistors R5 and R6 plus thevoltage drop across R14 (I5×R14).

The base transistor Q9 is biased by a bias circuit which provided anoptimum base-emitter voltage and optimum impedance. PNP transistor Q11has an emitter connected to the supply VCC and a collector connected toa current source by way of a resistor R4. Since the base current of Q11is relatively small, most of the current into current source I3 is byway of resistor R4. Inspection of the circuit shows that the voltage atthe collector of Q11, the thevenin equivalent output voltage of the biascircuit, is the base-emitter voltage of Q11 less the voltage drop acrossR4 produced by current I3. The output impedance of the bias circuit isapproximately equal to the resistance of R3 plus the output impedance oftransistor Q11. Output transistor Q9 is much larger, typically a fewhundred times larger, the Q11. Thus, in order to bias Q9 with abase-emitter voltage so that Q9 conducts a desired quiescent current,typically on the order of 100 μA, it is necessary for the base-emittervoltage of Q11 to be reduced by some factor, typically by a 100 mV dropacross resistor R4. The output impedance R of the bias circuit isselected such that the impedance in combination with Miller compensationcapacitor C3 produce a pole at a frequency F=1/(2π R C3) as a frequencythat is approximately 2 to 3 times the overall unity-gain frequency ofthe amplifier. The impedance is thus high enough so that the Millercompensation capacitor C3 can be effective. Further, the impedance islow enough such that settling time and slew performance are good.

One important aspect of the output stage of FIG. 2 is that there is onlya single PNP transistor, Q9, in the forward signal path. Since PNPtransistors usually have a lower F_(T) (unity current gain-bandwidthproduct) and a lower β than an NPN transistor, performance is enhanced.

The FIG. 2 circuit is compensated by the Miller capacitor C3 andresistor R11 and by capacitor C2 and resistor R7. Unlike the prior artcircuit of FIG. 1C, the impedance presented by resistor R3 andassociated circuitry is large enough to make the Miller compensationcapacitor C3 effective. Compensation capacitor C3 and R8 are optional.

FIG. 6 shows an alternative connection for transistors Q7, Q9 and Q10for limiting the current gain of the output stage when sourcing current.Rather than having the collector of Q10 connected to the emitter oftransistor Q7 as shown in FIG. 2, transistor Q10 is diode-connected,with the collector/base of Q10 being connected to the collector of Q7.Transistors Q1O and Q9 operate together to form a current mirror, withthe ratio of current between Q9 and Q10 effectively controlling thecurrent gain of Q9. The current ratio of the two transistors isinversely related to the ratio of the emitter areas of Q9 and Q10, withQ9 typically being ten times larger than Q10. Thus, the effectivecurrent gain remains fixed at ten, a gain much lower than the typicalcurrent gain β of Q9 alone. Accordingly, the current gains for sourcingand sinking current are more closely matched thereby causing the circuitoperation to be more stable. Note that resistor R9 in the FIG. 6embodiment performs a function in addition to compensating for thepresence of transistor Q9 ballast resistors R12. Resistor R9 increasesthe impedance at the base of transistor Q9 thereby rendering the Millercompensation capacitor C3 (FIG. 2) effective.

Referring again to the FIG. 2 circuit, during normal operation, outputvoltage Vout is driven towards supply VCC so that transistor Q9 will bedriven into saturation. Typically, the amplifier feedback action willattempt to force Vout to be equal to VCC, but no matter how much thebase drive is increased, the saturation voltage will always be greaterthan zero. Further, the current gain or β of Q9 will decreasesubstantially as a result so that a large base drive current for Q9 willbe required to support a given output current. Further, many types oftransistor structures made using junction-isolated processes haveparasitic transistors which can turn on during saturation. Theseparasitic transistors may cause latchup and unpredictable IC behavior asa result. In order to reduce the magnitude of the base drive current andto conserve power, and in order to prevent possible latchup with respectto transistor Q9, saturation control circuitry is provided for outputtransistors Q8 and Q9.

Although not depicted, a conventional inverted mode transistor isconnected across the base-collector junction of transistor Q8 whichprevents the base-collector junction from being forward biased therebykeeping the transistor out of saturation. The base and collector of theinverted mode transistor are connected to the base and collector,respectively, of Q8, with the emitter of the inverted mode transistorbeing connected to the base of Q6.

The circuitry for limiting the saturation of transistor Q9 takesadvantage of the junction-isolated vertical structure of the PNPtransistor. FIG. 4 is a schematic illustration of a cross-section of inintegrated circuit incorporating a PNP transistor such as Q9. Thestructure includes a P substrate 20 and an N type epitaxial layer 24. AnN well 26 is formed in substrate followed by a P well 28 formed in theepitaxial layer 26 and substrate 20. A collector C contact for the PNPis formed in the P well 28 by way of P diffusion 34. An N region 30 isformed in the P well 28 to create the base B of the PNP, with the Pregion 32 formed in the N region 30 functioning as the emitter E of thetransistor.

As previously noted, PNP transistor Q9 includes the desired transistorQ9A and a parasitic NPN transistor Q9X. The N type base region 30 formsthe “emitter” of Q9X, the P well 28 forms the “base” and N well 26 formsthe “collector”. FIG. 5 is a schematic diagram showing the electricalrelationship between desired transistor Q9A and the parasitic transistorQ9X. As can be see from FIG. 5, there is also a parasitic PNP transistorQ9Y having an “emitter” formed by t he P well 28, a “base” formed by theN well 26 and a “collector” formed by the substrate 20.

When the desired PNP transistor Q9A is driven into saturation, thecollector-base junction becomes forward biased. If the forward biasingvoltage is large enough, the “base-emitter” junction of parasitictransistor Q9X becomes forward biased thereby tuning the normally-offparasitic transistor Q9X on. This causes some of the base drive currentfor Q9 to be diverted to the N well 26 in the form of well currentI_(W). This current will cause a voltage to be developed across the Nwell parasitic resistance R_(W) having a polarity which will tend toforward bias parasitic transistor Q9Y. As desired transistor Q9A isdriven deeper into saturation, current I_(W) will increase until onebase-emitter voltage is developed across parasitic resistance R_(W)thereby turning on parasitic PNP transistor Q9Y. This causes currentflow from the upper supply VCC connected to the emitter of Q9A to thelower supply VEE connected to substrate 20, a current which can greatlyexceed the quiescent current of the output stage. Thus, it is importantto control the saturation limit of transistor Q9 so that the transistorwill be deep enough into saturation to permit Vout swing up close toupper supply VCC and not so deep as to turn on the parasitic PNPtransistors.

Saturation of transistor Q9 is controlled by monitoring the N wellcurrent I_(W) of the transistor, that is, the current flow into thecollector of parasitic transistor Q9X. The magnitude of this current isa function of the degree of forward bias of the base-collector junctionof parasitic transistor Q9Y which represents the degree to which thetransistor Q9Y is saturated.

As can be seen in FIG. 2, the N well of output transistor Q9 isconnected to the node intermediate resistor R1A and transistor Q3A. Whentransistor Q9 is driven hard so that Vout approaches supply VCC, thetransistor begins to saturate. As a result, current I_(W) will begin toincrease thereby decreasing the emitter voltage of transistor Q3A. Thiswill cause the transistors Q5 and Q7 to begin to turn off therebylimiting base drive to Q9. Well current I_(W) will no longer increasethereby allowing Q9 to remain saturated, but not so deeply saturatedthat parasitic transistor Q9Y (FIG. 5) is turned on.

The collector-to-N well capacitance of output transistor Q9 can berelatively large. The saturation control connection from Q9 back to Q3Aprovides a positive AC feedback path which requires compensation.Capacitor C4 connected between the node intermediate the emitter oftransistor Q14 and resistor R14 and the negative supply voltage VEEcompensates for the parasitic capacitance of Q9. Capacitor C5 connectedbetween the node intermediate Q3B and resistor R1B and negative supplyVEE compensates for the effect of capacitor C4. Ideally, capacitor C4 isa junction capacitor made to track the parasitic capacitance of Q9.

Thus, a novel output stage having high voltage swing capability has beendisclosed. Although one embodiment has been described in some detail, itis to be understood that certain changes can be made by those skilled inthe art without departing from the spirit and scope of the invention asdefined by the appended claims.

What is claimed is:
 1. An amplifier output stage of an amplifier, saidoutput stage comprising: a first PNP transistor having a collectorcoupled to an amplifier output and an emitter coupled to a first powersupply rail; a second NPN transistor having a base for receiving aninput signal and a collector coupled to a base of the first PNPtransistor; a first frequency compensation capacitor having one terminalcoupled to the collector of the first PNP transistor; and a bias circuitconfigured to provide a thevenin equivalent bias voltage having anassociated output impedance, with the bias circuit coupled to the baseof the first PNP transistor so that the first PNP transistor willconduct a desired quiescent current, with the equivalent bias voltagebeing independent of current flow in the first PNP transistor, and withthe output impedance being sufficiently large to form a pole incombination with the frequency compensation capacitor at a frequencybeyond a unity-gain frequency of the amplifier.
 2. The amplifier outputstage of claim 1 wherein the bias circuit includes a semiconductordevice having a PN junction which produces a PN junction voltage, withthe equivalent bias voltage being a fraction of the PN junction voltage.3. The amplifier output stage of claim 2 wherein the semiconductordevice is a third transistor and the PN junction voltage is abase-emitter junction voltage.
 4. The amplifier output stage of claim 3wherein the bias circuit includes a first resistor coupled relative tothe third transistor so the equivalent bias voltage is the differencebetween a voltage developed across the first resistor and thebase-emitter voltage of the third transistor.
 5. The amplifier outputstage of claim 4 wherein the first resistor is coupled between the baseand collector of the third transistor.
 6. The amplifier output stage ofclaim 5 wherein the bias circuit further includes a second resistorconnected between the first resistor and the base of the first PNPtransistor.
 7. The amplifier output stage of claim 3 further including afourth PNP transistor having a base coupled to a base of the firsttransistor and a collector coupled to the second transistor.
 8. Theamplifier output stage of claim 7 wherein the collector of the fourthPNP transistor is coupled to an emitter of the second NPN transistor. 9.The amplifier output stage of claim 8 wherein a first resistor isconnected intermediate the emitter of the second NPN transistor and asecond power supply rail and wherein the collector of the fourth PNPtransistor is coupled to a node intermediate the emitter of the secondNPN transistor and the first resistor.
 10. The amplifier output stage ofclaim 1 further including a third PNP transistor having a base coupledto the base of the first PNP transistor and a collector coupled to acollector of the second NPN transistor.
 11. The amplifier output stageof claim 10 further including a first resistor coupled intermediate theemitter of the third PNP transistor and the first power supply rail. 12.The amplifier output stage of claim 11 further including a secondresistor coupled intermediate the emitter of the first PNP transistorand the first power supply rail.
 13. The amplifier output stage of claim1 further including a third NPN transistor which provides the firstinput signal to the second NPN transistor, with the third NPN transistorhaving an emitter coupled to the base of the second NPN transistor. 14.The amplifier output stage of claim 13 further including a secondfrequency compensation capacitor coupled intermediate a base of thethird NPN transistor and the collector of the second NPN transistor. 15.The amplifier output stage of claim 14 further including a firstresistor connected in series with the first frequency compensationcapacitor and a second resistor connected in series with the secondfrequency compensation capacitor.
 16. An amplifier output stagecomprising: a first PNP transistor having a collector coupled to anamplifier output and an emitter coupled to a first power supply rail anda base; a second NPN transistor having a base for receiving an inputsignal and a collector coupled to a base of the first PNP transistor;and a bias circuit configured to produce a thevenin equivalent biasvoltage having an associated output impedance, with the bias circuitcoupled to the base of the first PNP transistor and including a thirdPNP transistor and a first resistor connected relative to the third PNPtransistor such that the equivalent bias voltage is equal to adifference in a base-emitter voltage of the third PNP transistor and avoltage drop across the first resistor, with the bias equivalent voltagehaving a magnitude which is smaller than a magnitude of the base-emittervoltage.
 17. The amplifier output stage of claim 16 wherein the firstresistor is connected between a collector and a base of the third PNPtransistor.
 18. The amplifier output stage of claim 17 wherein the biascircuit includes a current source connected to the first resistor so asto produce the voltage drop.
 19. The amplifier output stage of claim 18wherein the bias circuit further includes a second resistor having oneterminal coupled to a collector of the third PNP transistor and anotherterminal coupled to the base of the first PNP transistor.
 20. Theamplifier output stage of claim 16 includes a frequency compensationcapacitor and wherein the output impedance in combination with thecompensation capacitor produce a pole which is at a frequency in excessof the unity-gain frequency of an amplifier incorporating the outputstage.
 21. A method of biasing an amplifier output stage having a firstPNP transistor with an emitter coupled to a power supply rail and acollector coupled to an output of the amplifier output stage and afrequency compensation capacitor coupled to the first PNP transistor,said method comprising: generating a base-emitter voltage using a secondtransistor; generating a first voltage having a magnitude that isrelatively independent of current flow in the first PNP transistor;combining the base-emitter voltage and the first voltage to produce abias voltage equal to a difference between the base-emitter voltage andthe first voltage so that the bias voltage has a magnitude smaller thana magnitude of the base-emitter voltage; and coupling the bias voltagethrough an effective output impedance across the base-emitter junctionof the first PNP transistor.
 22. The method of claim 21 furtherincluding setting the effective output impedance so that the effectiveoutput impedance and a frequency compensation capacitor of the amplifieroutput stage produce a pole at a frequency in excess of a unity-gainfrequency of an amplifier in which the output stage is incorporated. 23.An amplifier output stage of an amplifier, said output stage comprising:a first PNP transistor having a collector coupled to an amplifier outputand an emitter coupled to a first power supply rail; a second NPNtransistor having a base for receiving an input signal and a collectorcoupled to a base of the first PNP transistor; a first frequencycompensation capacitor having one terminal coupled to the collector ofthe first PNP transistor; and a bias circuit coupled to the first PNPtransistor and configured to provide a therein equivalent bias voltagehaving an associated output impedance, with the bias circuit coupled toa base of the first PNP transistor so that the first PNP transistor willconduct a desired quiescent current, with said bias circuit beingdisposed outside a signal path defined by the base and collector of thesecond NPN transistor and the base and collector of the first PNPtransistor and with the output impedance being sufficiently large toform a pole in combination with the first frequency compensationcapacitor at a frequency beyond a unity-gain frequency of the amplifier.24. The amplifier output stage of claim 23 wherein the bias circuitincludes a semiconductor device having a PN junction which produces a PNjunction voltage, with the equivalent bias voltage being a fraction ofthe PN junction voltage.
 25. The amplifier output stage of claim 24wherein the semiconductor device is a third transistor and the PNjunction voltage is a base-emitter junction voltage.
 26. The amplifieroutput stage of claim 25 wherein the bias circuit includes a firstresistor coupled relative to the third transistor so the equivalent biasvoltage is the difference between a voltage developed across the firstresistor and the base-emitter voltage of the third transistor.
 27. Theamplifier output stage of claim 26 wherein the first resistor is coupledbetween the base and collector of the third transistor.
 28. Theamplifier output stage of claim 27 wherein the bias circuit furtherincludes a second resistor connected between the first resistor and thebase of the first PNP transistor.
 29. The amplifier output stage ofclaim 25 further including a fourth PNP transistor having a base coupledto a base of the first transistor and a collector coupled to the secondtransistor.
 30. The amplifier output stage of claim 29 wherein thecollector of the fourth PNP transistor is coupled to an emitter of thesecond NPN transistor.
 31. The amplifier output stage of claim 30wherein a first resistor is connected intermediate the emitter of thesecond PNP transistor and a second power supply rail and wherein thecollector of the fourth PNP transistor is coupled to a node intermediatethe emitter of the second NPN transistor and the first resistor.
 32. Theamplifier output stage of claim 23 further including a third PNPtransistor having a base coupled to the base of the first PNP transistorand a collector coupled to a collector of the second NPN transistor. 33.The amplifier output stage of claim 32 further including a firstresistor coupled intermediate the emitter of the third PNP transistorand the first power supply rail.
 34. The amplifier output stage of claim33 further including a second resistor coupled intermediate the emitterof the first PNP transistor and the first power supply rail.
 35. Theamplifier output stage of claim 23 further including a third NPNtransistor which provides the first input signal to the second NPNtransistor, with the third NPN transistor having an emitter coupled tothe base of the second NPN transistor.
 36. The amplifier output stage ofclaim 34 further including a second frequency compensation capacitorcoupled intermediate a base of the third NPN transistor and thecollector of the second NPN transistor.
 37. The amplifier output stageof claim 36 further including a first resistor connected in series withthe first frequency compensation capacitor and a second resistorconnected in series with the second frequency compensation capacitor.